AXP1xxIrq.hpp

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#pragma once
#include "../../PmicIrqBase.hpp"
#include "../../../platform/SensorCommWrapper.hpp"
 
template<typename Regs>
class AXP1xxIrq : public PmicIrqBase
{
public:
    // ========================================================================
    // INTSTS1 -> bits 0-7  (STATUS1: AXP192=REG44H, AXP202=REG48H)
    // All shared [AXP192+AXP202]
    // ========================================================================
    static constexpr uint64_t IRQ_ACIN_OV           = (1ULL << 7);
    static constexpr uint64_t IRQ_ACIN_INSERT        = (1ULL << 6);
    static constexpr uint64_t IRQ_ACIN_REMOVE        = (1ULL << 5);
    static constexpr uint64_t IRQ_VBUS_OV            = (1ULL << 4);
    static constexpr uint64_t IRQ_VBUS_INSERT        = (1ULL << 3);
    static constexpr uint64_t IRQ_VBUS_REMOVE        = (1ULL << 2);
    static constexpr uint64_t IRQ_VBUS_LOW_VHOLD     = (1ULL << 1);
 
    // ========================================================================
    // INTSTS2 -> bits 8-15  (STATUS2: AXP192=REG45H, AXP202=REG49H)
    // All shared [AXP192+AXP202]
    // ========================================================================
    static constexpr uint64_t IRQ_BAT_INSERT         = (1ULL << 15);
    static constexpr uint64_t IRQ_BAT_REMOVE         = (1ULL << 14);
    static constexpr uint64_t IRQ_BAT_ENTER_ACTIVATE = (1ULL << 13);
    static constexpr uint64_t IRQ_BAT_EXIT_ACTIVATE  = (1ULL << 12);
    static constexpr uint64_t IRQ_BAT_CHG_START      = (1ULL << 11);
    static constexpr uint64_t IRQ_BAT_CHG_DONE       = (1ULL << 10);
    static constexpr uint64_t IRQ_BAT_TEMP_HIGH      = (1ULL << 9);
    static constexpr uint64_t IRQ_BAT_TEMP_LOW       = (1ULL << 8);
 
    // ========================================================================
    // INTSTS3 -> bits 16-23  (STATUS3: AXP192=REG46H, AXP202=REG4AH)
    // ========================================================================
    static constexpr uint64_t IRQ_CHIP_OV_TEMP       = (1ULL << 23);
    static constexpr uint64_t IRQ_CHG_CURR_LESS      = (1ULL << 22);
    static constexpr uint64_t IRQ_DC1_VOLT_LESS      = (1ULL << 21);
    static constexpr uint64_t IRQ_DC2_VOLT_LESS      = (1ULL << 20);
    static constexpr uint64_t IRQ_DC3_VOLT_LESS      = (1ULL << 19);
    // NOTE: STATUS3 bit 2 is Reserved on both AXP192 (REG46H[2]) and
    // AXP202 (REG4AH[2]).
    static constexpr uint64_t IRQ_PEKEY_SHORT_PRESS  = (1ULL << 17);
    static constexpr uint64_t IRQ_PEKEY_LONG_PRESS   = (1ULL << 16);
 
    // ========================================================================
    // INTSTS4 -> bits 24-31  (STATUS4: AXP192=REG47H, AXP202=REG4BH)
    // ========================================================================
    static constexpr uint64_t IRQ_NOE_POWERON        = (1ULL << 31);
    static constexpr uint64_t IRQ_NOE_POWERDOWN      = (1ULL << 30);
    static constexpr uint64_t IRQ_VBUS_EFFECTIVE     = (1ULL << 29);
    static constexpr uint64_t IRQ_VBUS_INVALID       = (1ULL << 28);
    static constexpr uint64_t IRQ_VBUS_SESSION       = (1ULL << 27);
    static constexpr uint64_t IRQ_VBUS_SESSION_END   = (1ULL << 26);
    static constexpr uint64_t IRQ_LOW_VOLT_LEVEL1    = (1ULL << 25);
    static constexpr uint64_t IRQ_LOW_VOLT_LEVEL2    = (1ULL << 24);
 
    // ========================================================================
    // INTSTS5 -> bits 32-39  (STATUS5: AXP192=REG4DH, AXP202=REG4CH)
    // ========================================================================
    static constexpr uint64_t IRQ_GPIO0_EDGE         = (1ULL << 32);
    static constexpr uint64_t IRQ_GPIO1_EDGE         = (1ULL << 33);
    static constexpr uint64_t IRQ_GPIO2_EDGE         = (1ULL << 34);
    static constexpr uint64_t IRQ_GPIO3_EDGE         = (1ULL << 35);
    static constexpr uint64_t IRQ_PKEY_NEGATIVE      = (1ULL << 37);
    static constexpr uint64_t IRQ_PKEY_POSITIVE      = (1ULL << 38);
    static constexpr uint64_t IRQ_TIMER_TIMEOUT      = (1ULL << 39);
 
    static constexpr uint64_t IRQ_ALL_MASK           = 0xFFFFFFFFFFULL;
 
    // *INDENT-OFF*
    static bool isIrqSet(uint64_t irqMask, uint64_t status) { return (status & irqMask) != 0; }
 
    // ========================================================================
    // INTSTS1 interrupt check functions [AXP192+AXP202]
    // ========================================================================
    static bool isAcinOv(uint64_t m) { return isIrqSet(IRQ_ACIN_OV, m); }
    static bool isAcinInsert(uint64_t m) { return isIrqSet(IRQ_ACIN_INSERT, m); }
    static bool isAcinRemove(uint64_t m) { return isIrqSet(IRQ_ACIN_REMOVE, m); }
    static bool isVbusOv(uint64_t m) { return isIrqSet(IRQ_VBUS_OV, m); }
    static bool isVbusInsert(uint64_t m) { return isIrqSet(IRQ_VBUS_INSERT, m); }
    static bool isVbusRemove(uint64_t m) { return isIrqSet(IRQ_VBUS_REMOVE, m); }
    static bool isVbusLowVhold(uint64_t m) { return isIrqSet(IRQ_VBUS_LOW_VHOLD, m); }
 
    // ========================================================================
    // INTSTS2 interrupt check functions [AXP192+AXP202]
    // ========================================================================
    static bool isBatInsert(uint64_t m) { return isIrqSet(IRQ_BAT_INSERT, m); }
    static bool isBatRemove(uint64_t m) { return isIrqSet(IRQ_BAT_REMOVE, m); }
    static bool isBatEnterActivate(uint64_t m) { return isIrqSet(IRQ_BAT_ENTER_ACTIVATE, m); }
    static bool isBatExitActivate(uint64_t m) { return isIrqSet(IRQ_BAT_EXIT_ACTIVATE, m); }
    static bool isBatChgStart(uint64_t m) { return isIrqSet(IRQ_BAT_CHG_START, m); }
    static bool isBatChgDone(uint64_t m) { return isIrqSet(IRQ_BAT_CHG_DONE, m); }
    static bool isBatTempHigh(uint64_t m) { return isIrqSet(IRQ_BAT_TEMP_HIGH, m); }
    static bool isBatTempLow(uint64_t m) { return isIrqSet(IRQ_BAT_TEMP_LOW, m); }
 
    // ========================================================================
    // INTSTS3 interrupt check functions [AXP192+AXP202]
    // ========================================================================
    static bool isChipOvTemp(uint64_t m) { return isIrqSet(IRQ_CHIP_OV_TEMP, m); }
    static bool isChgCurrLess(uint64_t m) { return isIrqSet(IRQ_CHG_CURR_LESS, m); }
    static bool isDc1VoltLess(uint64_t m) { return isIrqSet(IRQ_DC1_VOLT_LESS, m); }
    static bool isDc2VoltLess(uint64_t m) { return isIrqSet(IRQ_DC2_VOLT_LESS, m); }
    static bool isDc3VoltLess(uint64_t m) { return isIrqSet(IRQ_DC3_VOLT_LESS, m); }
    static bool isPekeyShortPress(uint64_t m) { return isIrqSet(IRQ_PEKEY_SHORT_PRESS, m); }
    static bool isPekeyLongPress(uint64_t m) { return isIrqSet(IRQ_PEKEY_LONG_PRESS, m); }
 
    // ========================================================================
    // INTSTS4 interrupt check functions
    // ========================================================================
    static bool isNoePoweron(uint64_t m) { return isIrqSet(IRQ_NOE_POWERON, m); }
    static bool isNoePowerdown(uint64_t m) { return isIrqSet(IRQ_NOE_POWERDOWN, m); }
    static bool isVbusEffective(uint64_t m) { return isIrqSet(IRQ_VBUS_EFFECTIVE, m); }
    static bool isVbusInvalid(uint64_t m) { return isIrqSet(IRQ_VBUS_INVALID, m); }
    static bool isVbusSession(uint64_t m) { return isIrqSet(IRQ_VBUS_SESSION, m); }
    static bool isVbusSessionEnd(uint64_t m) { return isIrqSet(IRQ_VBUS_SESSION_END, m); }
    static bool isLowVoltLevel2(uint64_t m) { return isIrqSet(IRQ_LOW_VOLT_LEVEL2, m); }
    static bool isLowVoltLevel1(uint64_t m) { return isIrqSet(IRQ_LOW_VOLT_LEVEL1, m); }
 
    // ========================================================================
    // INTSTS5 interrupt check functions
    // ========================================================================
    static bool isGpio0EdgeTrigger(uint64_t m) { return isIrqSet(IRQ_GPIO0_EDGE, m); }
    static bool isGpio1EdgeTrigger(uint64_t m) { return isIrqSet(IRQ_GPIO1_EDGE, m); }
    static bool isGpio2EdgeTrigger(uint64_t m) { return isIrqSet(IRQ_GPIO2_EDGE, m); }
    static bool isGpio3EdgeTrigger(uint64_t m) { return isIrqSet(IRQ_GPIO3_EDGE, m); }
    static bool isPkeyNegative(uint64_t m) { return isIrqSet(IRQ_PKEY_NEGATIVE, m); }
    static bool isPkeyPositive(uint64_t m) { return isIrqSet(IRQ_PKEY_POSITIVE, m); }
    static bool isTimerTimeout(uint64_t m) { return isIrqSet(IRQ_TIMER_TIMEOUT, m); }
 
    // ========================================================================
    // AXP192 naming aliases (legacy XPowersLib compatibility)
    // ========================================================================
    static bool isAcinOverVol(uint64_t m) { return isAcinOv(m); }
    static bool isAcinConnect(uint64_t m) { return isAcinInsert(m); }
    static bool isVbusOverVol(uint64_t m) { return isVbusOv(m); }
    static bool isVbusVholdLow(uint64_t m) { return isVbusLowVhold(m); }
    static bool isBattActivate(uint64_t m) { return isBatEnterActivate(m); }
    static bool isBattExitActivate(uint64_t m) { return isBatExitActivate(m); }
    static bool isBattOverTemp(uint64_t m) { return isBatTempHigh(m); }
    static bool isBattLowTemp(uint64_t m) { return isBatTempLow(m); }
    static bool isChipTempHigh(uint64_t m) { return isChipOvTemp(m); }
    static bool isChargeLowCur(uint64_t m) { return isChgCurrLess(m); }
    static bool isDc1LowVol(uint64_t m) { return isDc1VoltLess(m); }
    static bool isDc2LowVol(uint64_t m) { return isDc2VoltLess(m); }
    static bool isDc3LowVol(uint64_t m) { return isDc3VoltLess(m); }
    // static bool isPkeyShortPress(uint64_t m) { return isPekeyShortPress(m); }
    // static bool isPkeyLongPress(uint64_t m) { return isPekeyLongPress(m); }
    static bool isNoeOn(uint64_t m) { return isNoePoweron(m); }
    static bool isNoeOff(uint64_t m) { return isNoePowerdown(m); }
    static bool isVbusValid(uint64_t m) { return isVbusEffective(m); }
    static bool isVbusSessionAB(uint64_t m) { return isVbusSession(m); }
    static bool isApsLowVolLevel(uint64_t m) { return isLowVoltLevel2(m); }
    static bool isGpio0Irq(uint64_t m) { return isGpio0EdgeTrigger(m); }
    static bool isGpio1Irq(uint64_t m) { return isGpio1EdgeTrigger(m); }
    static bool isGpio2Irq(uint64_t m) { return isGpio2EdgeTrigger(m); }
    static bool isTimerIrq(uint64_t m) { return isTimerTimeout(m); }
 
    // ========================================================================
    // AXP202 naming aliases (legacy XPowersLib compatibility)
    // ========================================================================
    static bool isApsLowVolLevel1(uint64_t m) { return isLowVoltLevel1(m); }
    static bool isGpio3Irq(uint64_t m) { return isGpio3EdgeTrigger(m); }
 
    // *INDENT-ON*
 
    explicit AXP1xxIrq(SensorCommWrapper &core) : _core(core) {}
 
    bool enable(uint64_t mask) override;
 
    bool disable(uint64_t mask) override;
 
    uint64_t readStatus(bool clear = true) override;
 
    bool clearStatus() override;
 
private:
    bool readEnableRegs(uint8_t buf[5]);
 
    bool writeEnableRegsIfChanged(const uint8_t before[5], const uint8_t after[5]);
 
    bool clearStatusByMask(const uint8_t maskBytes[5]);
 
    bool clearAllStatusRegs();
 
    static uint64_t pack5(const uint8_t buf[5]);
 
    static void unpack5(uint64_t val, uint8_t buf[5]);
 
    SensorCommWrapper &_core;
};
 
template<typename Regs>
bool AXP1xxIrq<Regs>::readEnableRegs(uint8_t buf[5])
{
    if (_core.readRegBuff(Regs::irq::ENABLE1, buf, 4) < 0) {
        return false;
    }
 
    int en5 = _core.readReg(Regs::irq::ENABLE5);
    if (en5 < 0) {
        return false;
    }
    buf[4] = static_cast<uint8_t>(en5);
    return true;
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::writeEnableRegsIfChanged(const uint8_t before[5], const uint8_t after[5])
{
    // Warning: It cannot be optimized to continuous writing, otherwise an error will occur.
    for (int i = 0; i < 4; ++i) {
        if (before[i] != after[i]) {
            if (_core.writeReg(Regs::irq::ENABLE1 + i, after[i]) < 0) {
                return false;
            }
        }
    }
 
    if (before[4] != after[4]) {
        if (_core.writeReg(Regs::irq::ENABLE5, after[4]) < 0) {
            return false;
        }
    }
    return true;
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::clearStatusByMask(const uint8_t maskBytes[5])
{
    // Warning: It cannot be optimized to continuous writing, otherwise an error will occur.
    for (int i = 0; i < 4; ++i) {
        if (maskBytes[i] != 0) {
            if (_core.writeReg(Regs::irq::STATUS1 + i, maskBytes[i]) < 0) {
                return false;
            }
        }
    }
 
    if (maskBytes[4] != 0) {
        if (_core.writeReg(Regs::irq::STATUS5, maskBytes[4]) < 0) {
            return false;
        }
    }
    return true;
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::clearAllStatusRegs()
{
    const uint8_t all[5] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
    return clearStatusByMask(all);
}
 
template<typename Regs>
inline uint64_t AXP1xxIrq<Regs>::pack5(const uint8_t buf[5])
{
    return (static_cast<uint64_t>(buf[0])) |
           (static_cast<uint64_t>(buf[1]) << 8) |
           (static_cast<uint64_t>(buf[2]) << 16) |
           (static_cast<uint64_t>(buf[3]) << 24) |
           (static_cast<uint64_t>(buf[4]) << 32);
}
 
template<typename Regs>
inline void AXP1xxIrq<Regs>::unpack5(uint64_t val, uint8_t buf[5])
{
    buf[0] = static_cast<uint8_t>(val & 0xFF);
    buf[1] = static_cast<uint8_t>((val >> 8) & 0xFF);
    buf[2] = static_cast<uint8_t>((val >> 16) & 0xFF);
    buf[3] = static_cast<uint8_t>((val >> 24) & 0xFF);
    buf[4] = static_cast<uint8_t>((val >> 32) & 0xFF);
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::enable(uint64_t mask)
{
    uint8_t before[5], after[5];
    if (!readEnableRegs(before)) {
        return false;
    }
 
    uint64_t current = pack5(before);
    current |= mask;
    unpack5(current, after);
 
    return writeEnableRegsIfChanged(before, after);
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::disable(uint64_t mask)
{
    uint8_t before[5], after[5];
    if (!readEnableRegs(before)) {
        return false;
    }
 
    uint64_t current = pack5(before);
    current &= ~mask;
    unpack5(current, after);
 
    return writeEnableRegsIfChanged(before, after);
}
 
template<typename Regs>
uint64_t AXP1xxIrq<Regs>::readStatus(bool clear)
{
    uint8_t buf[5];
    if (_core.readRegBuff(Regs::irq::STATUS1, buf, 4) < 0) {
        return 0;
    }
    int st5 = _core.readReg(Regs::irq::STATUS5);
    if (st5 < 0) return 0;
    buf[4] = static_cast<uint8_t>(st5);
 
    uint64_t mask = pack5(buf);
    if (clear && mask != 0) {
        // W1C safe: only write back the bits that were actually read,
        // so newly arrived interrupts between read and clear are preserved.
        if (!clearStatusByMask(buf)) {
            return 0;
        }
    }
    return mask;
}
 
template<typename Regs>
bool AXP1xxIrq<Regs>::clearStatus()
{
    return clearAllStatusRegs();
}