AXP202PowerEx.hpp

Go to the documentation of this file.

 
#pragma once
#include "AXP202Core.hpp"
#include "AXP202Regs.hpp"
 
class AXP202PowerEx
{
public:
    enum class LDO3Mode : uint8_t {
        LDO = 0,
        DCIN = 1,
    };
 
    explicit AXP202PowerEx(AXP202Core &core) : _core(core) {}
 
    // ---- Power Key Configuration (REG 36H) ----
 
    void enableLongPressShutdown()
    {
        _core.setRegBit(axp202_regs::pmu::POK_SET, 3);
    }
 
    void disableLongPressShutdown()
    {
        _core.clrRegBit(axp202_regs::pmu::POK_SET, 3);
    }
 
    // ---- LDO3 Operating Mode (REG 29H) ----
 
    bool setLDO3Mode(LDO3Mode mode)
    {
        switch (mode) {
        case LDO3Mode::LDO:
            return _core.clrRegBit(axp202_regs::pmu::LDO3OUT_VOL, 7);
        case LDO3Mode::DCIN:
            return _core.setRegBit(axp202_regs::pmu::LDO3OUT_VOL, 7);
        default:
            return false;
        }
    }
 
    // ---- DCDC Operating Mode (REG 80H) ----
 
    bool setDCDC2PWMMode(bool pwm)
    {
        return pwm ? _core.setRegBit(axp202_regs::pmu::DCDC_MODESET, 2)
               : _core.clrRegBit(axp202_regs::pmu::DCDC_MODESET, 2);
    }
 
    bool isDCDC2PWMMode()
    {
        return _core.getRegBit(axp202_regs::pmu::DCDC_MODESET, 2);
    }
 
    bool setDCDC3PWMMode(bool pwm)
    {
        return pwm ? _core.setRegBit(axp202_regs::pmu::DCDC_MODESET, 1)
               : _core.clrRegBit(axp202_regs::pmu::DCDC_MODESET, 1);
    }
 
    bool isDCDC3PWMMode()
    {
        return _core.getRegBit(axp202_regs::pmu::DCDC_MODESET, 1);
    }
 
    // ---- APS Warning Thresholds (REG 3AH, 3BH) ----
 
    bool setAPSWarningLevel1(uint8_t opt)
    {
        return _core.updateBits(axp202_regs::pmu::APS_WARNING1, 0xFF, opt) >= 0;
    }
 
    uint8_t getAPSWarningLevel1()
    {
        int val = _core.readReg(axp202_regs::pmu::APS_WARNING1);
        return (val < 0) ? 0 : static_cast<uint8_t>(val & 0xFF);
    }
 
    bool setAPSWarningLevel2(uint8_t opt)
    {
        return _core.updateBits(axp202_regs::pmu::APS_WARNING2, 0xFF, opt) >= 0;
    }
 
    uint8_t getAPSWarningLevel2()
    {
        int val = _core.readReg(axp202_regs::pmu::APS_WARNING2);
        return (val < 0) ? 0 : static_cast<uint8_t>(val & 0xFF);
    }
 
    // ---- Over-Temperature Shutdown (REG 8FH) ----
 
    bool enableOverTemperatureShutdown(bool enable)
    {
        return enable ? _core.setRegBit(axp202_regs::pmu::HOTOVER_CTL, 2)
               : _core.clrRegBit(axp202_regs::pmu::HOTOVER_CTL, 2);
    }
 
    bool isOverTemperatureShutdownEnabled()
    {
        return _core.getRegBit(axp202_regs::pmu::HOTOVER_CTL, 2);
    }
 
    // ---- DCDC Frequency (REG 37H) ----
    bool setDCDCFrequency(uint8_t freq)
    {
        return _core.writeReg(axp202_regs::pmu::DCDC_FREQSET, freq) >= 0;
    }
 
    uint8_t getDCDCFrequency()
    {
        int val = _core.readReg(axp202_regs::pmu::DCDC_FREQSET);
        return (val < 0) ? 0 : static_cast<uint8_t>(val);
    }
 
    // ---- VBUS Detection/SRP (REG 8BH) ----
 
    bool enableVBUSDetection(bool enable)
    {
        return enable ? _core.setRegBit(axp202_regs::pmu::VBUS_DET_SRP, 3)
               : _core.clrRegBit(axp202_regs::pmu::VBUS_DET_SRP, 3);
    }
 
    bool isVBUSDetectionEnabled()
    {
        return _core.getRegBit(axp202_regs::pmu::VBUS_DET_SRP, 3);
    }
 
private:
    AXP202Core &_core;
};