SensorLib 0.5.0
Multi-platform sensor driver library for Arduino, PlatformIO, and ESP-IDF
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HapticDriver_AW86224_Reg.hpp
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1
30#pragma once
31
32#include <stdint.h>
33
34namespace AW86224Regs
35{
36
37
38static constexpr uint8_t SOFTRESET_VAL = 0xAA;
39
40static constexpr uint32_t EN_RAMINIT = 0x08;
41static constexpr uint32_t VBAT_GO = 0x02;
42
43static constexpr uint8_t PLAYCFG4_GO_ON = 0x01;
44static constexpr uint8_t PLAYCFG4_STOP_ON = 0x02;
45
46static constexpr uint8_t MASK_GLB_STATE = 0x0F;
47static constexpr uint8_t STATE_STANDBY = 0;
48static constexpr uint8_t STATE_RTP_GO = 8;
49
50static constexpr uint8_t WAVLOOP_INIFINITELY = 0x0F;
51
52static constexpr uint16_t AW_VBAT_MIN = 3000;
53static constexpr uint16_t AW_VBAT_REFER = 4200;
54static constexpr uint8_t AW_DEFAULT_GAIN = 0x80;
55
56static constexpr uint8_t IRQ_NULL = 0;
57static constexpr uint8_t IRQ_UVL = 1;
58static constexpr uint8_t IRQ_OCD = 2;
59static constexpr uint8_t IRQ_OT = 3;
60static constexpr uint8_t IRQ_DONE = 4;
61static constexpr uint8_t IRQ_ALMOST_FULL = 5;
62static constexpr uint8_t IRQ_ALMOST_EMPTY = 6;
63
64static constexpr uint8_t CONT_VBAT_SW_COMP_MODE = 0;
65static constexpr uint8_t CONT_VBAT_HW_COMP_MODE = 1;
66
67static constexpr uint16_t F0_PRE_VAL = 1700;
68static constexpr uint16_t LRA_VRMS_VAL = 1000;
69static constexpr uint8_t CONT_BRK_TIME_VAL = 0x06;
70static constexpr uint8_t CONT_BRK_GAIN_VAL = 0x08;
71static constexpr uint8_t D2S_GAIN_VAL = 0x05;
72static constexpr uint8_t PWMCFG4_PRTIME_VAL = 0x32;
73static constexpr uint8_t PWMCFG3_PRLVL_VAL = 0x3F;
74static constexpr uint8_t CONT_DRV1_LVL_VAL = 0x7F;
75static constexpr uint8_t F0_CALI_ACCURACY = 24;
76static constexpr uint8_t CONT_DRV1_TIME_VAL = 0x04;
77static constexpr uint8_t CONT_DRV2_TIME_VAL = 0x14;
78static constexpr uint8_t CONT_TRACK_MARGIN_VAL = 0x0F;
79static constexpr uint8_t GAIN_BYPASS_CHANGEABLE = 0x40;
80
81static constexpr uint8_t INT_MODE_EDGE = 0x10;
82static constexpr uint8_t INT_EDGE_MODE_POS = 0;
83
84
85// ==============================================
86// 0x00 (WO)
87// ==============================================
88// Register : SRST
89static constexpr uint8_t REG_SRST = 0x00;
90static constexpr uint8_t MASK_RESET = 0xFF; // write 0xAA to reset
91
92// ==============================================
93// 0x01 (RO)
94// ==============================================
95// Register : SYSST
96static constexpr uint8_t REG_SYSST = 0x01;
97static constexpr uint8_t MASK_DONES = 0x01;
98static constexpr uint8_t MASK_OTS = 0x02;
99static constexpr uint8_t MASK_OCDS = 0x04;
100static constexpr uint8_t MASK_FF_AFS = 0x08;
101static constexpr uint8_t MASK_FF_AES = 0x10;
102static constexpr uint8_t MASK_UVLS = 0x20;
103
104// ==============================================
105// 0x02 (RC)
106// ==============================================
107// Register : SYSINT
108static constexpr uint8_t REG_SYSINT = 0x02;
109static constexpr uint8_t MASK_DONEI = 0x01;
110static constexpr uint8_t MASK_OTI = 0x02;
111static constexpr uint8_t MASK_OCDI = 0x04;
112static constexpr uint8_t MASK_FF_AFI = 0x08;
113static constexpr uint8_t MASK_FF_AEI = 0x10;
114static constexpr uint8_t MASK_UVLI = 0x20;
115
116// ==============================================
117// 0x03 (RW)
118// ==============================================
119// Register : SYSINTM
120static constexpr uint8_t REG_SYSINTM = 0x03;
121static constexpr uint8_t MASK_DONEM = 0x01;
122static constexpr uint8_t MASK_OTM = 0x02;
123static constexpr uint8_t MASK_OCDM = 0x04;
124static constexpr uint8_t MASK_FF_AFM = 0x08;
125static constexpr uint8_t MASK_FF_AEM = 0x10;
126static constexpr uint8_t MASK_UVLM = 0x20;
127
128// ==============================================
129// 0x04 (RO)
130// ==============================================
131// Register : SYSST2
132static constexpr uint8_t REG_SYSST2 = 0x04;
133static constexpr uint8_t MASK_LDO_OK = 0x08;
134
135// ==============================================
136// 0x07 (RW)
137// ==============================================
138// Register : PLAYCFG2
139static constexpr uint8_t REG_PLAYCFG2 = 0x07;
140static constexpr uint8_t MASK_GAIN = 0xFF;
141static constexpr uint8_t SHIFT_GAIN = 0;
142
143// ==============================================
144// 0x08 (RW)
145// ==============================================
146// Register : PLAYCFG3
147static constexpr uint8_t REG_PLAYCFG3 = 0x08;
148static constexpr uint8_t MASK_STOP_MODE = 0x20;
149static constexpr uint8_t MASK_BRK_EN = 0x04;
150static constexpr uint8_t MASK_PLAY_MODE = 0x03;
151static constexpr uint8_t SHIFT_PLAY_MODE = 0;
152
153// ==============================================
154// 0x09 (RW)
155// ==============================================
156// Register : PLAYCFG4
157static constexpr uint8_t REG_PLAYCFG4 = 0x09;
158static constexpr uint8_t MASK_STOP = 0x02;
159static constexpr uint8_t MASK_GO = 0x01;
160
161// ==============================================
162// 0x0A (RW)
163// ==============================================
164// Register : WAVCFG1
165static constexpr uint8_t REG_WAVCFG1 = 0x0A;
166static constexpr uint8_t MASK_SEQ1WAIT = 0x80;
167static constexpr uint8_t MASK_WAVSEQ1 = 0x7F;
168static constexpr uint8_t SHIFT_WAVSEQ1 = 0;
169
170// ==============================================
171// 0x0B (RW)
172// ==============================================
173// Register : WAVCFG2
174static constexpr uint8_t REG_WAVCFG2 = 0x0B;
175static constexpr uint8_t MASK_SEQ2WAIT = 0x80;
176static constexpr uint8_t MASK_WAVSEQ2 = 0x7F;
177static constexpr uint8_t SHIFT_WAVSEQ2 = 0;
178
179// ==============================================
180// 0x0C (RW)
181// ==============================================
182// Register : WAVCFG3
183static constexpr uint8_t REG_WAVCFG3 = 0x0C;
184static constexpr uint8_t MASK_SEQ3WAIT = 0x80;
185static constexpr uint8_t MASK_WAVSEQ3 = 0x7F;
186static constexpr uint8_t SHIFT_WAVSEQ3 = 0;
187
188// ==============================================
189// 0x0D (RW)
190// ==============================================
191// Register : WAVCFG4
192static constexpr uint8_t REG_WAVCFG4 = 0x0D;
193static constexpr uint8_t MASK_SEQ4WAIT = 0x80;
194static constexpr uint8_t MASK_WAVSEQ4 = 0x7F;
195static constexpr uint8_t SHIFT_WAVSEQ4 = 0;
196
197// ==============================================
198// 0x0E (RW)
199// ==============================================
200// Register : WAVCFG5
201static constexpr uint8_t REG_WAVCFG5 = 0x0E;
202static constexpr uint8_t MASK_SEQ5WAIT = 0x80;
203static constexpr uint8_t MASK_WAVSEQ5 = 0x7F;
204static constexpr uint8_t SHIFT_WAVSEQ5 = 0;
205
206// ==============================================
207// 0x0F (RW)
208// ==============================================
209// Register : WAVCFG6
210static constexpr uint8_t REG_WAVCFG6 = 0x0F;
211static constexpr uint8_t MASK_SEQ6WAIT = 0x80;
212static constexpr uint8_t MASK_WAVSEQ6 = 0x7F;
213static constexpr uint8_t SHIFT_WAVSEQ6 = 0;
214
215// ==============================================
216// 0x10 (RW)
217// ==============================================
218// Register : WAVCFG7
219static constexpr uint8_t REG_WAVCFG7 = 0x10;
220static constexpr uint8_t MASK_SEQ7WAIT = 0x80;
221static constexpr uint8_t MASK_WAVSEQ7 = 0x7F;
222static constexpr uint8_t SHIFT_WAVSEQ7 = 0;
223
224// ==============================================
225// 0x11 (RW)
226// ==============================================
227// Register : WAVCFG8
228static constexpr uint8_t REG_WAVCFG8 = 0x11;
229static constexpr uint8_t MASK_SEQ8WAIT = 0x80;
230static constexpr uint8_t MASK_WAVSEQ8 = 0x7F;
231static constexpr uint8_t SHIFT_WAVSEQ8 = 0;
232
233// ==============================================
234// 0x12 (RW)
235// ==============================================
236// Register : WAVCFG9
237static constexpr uint8_t REG_WAVCFG9 = 0x12;
238static constexpr uint8_t MASK_SEQ1LOOP = 0xF0;
239static constexpr uint8_t SHIFT_SEQ1LOOP = 4;
240static constexpr uint8_t MASK_SEQ2LOOP = 0x0F;
241static constexpr uint8_t SHIFT_SEQ2LOOP = 0;
242
243// ==============================================
244// 0x13 (RW)
245// ==============================================
246// Register : WAVCFG10
247static constexpr uint8_t REG_WAVCFG10 = 0x13;
248static constexpr uint8_t MASK_SEQ3LOOP = 0xF0;
249static constexpr uint8_t SHIFT_SEQ3LOOP = 4;
250static constexpr uint8_t MASK_SEQ4LOOP = 0x0F;
251static constexpr uint8_t SHIFT_SEQ4LOOP = 0;
252
253// ==============================================
254// 0x14 (RW)
255// ==============================================
256// Register : WAVCFG11
257static constexpr uint8_t REG_WAVCFG11 = 0x14;
258static constexpr uint8_t MASK_SEQ5LOOP = 0xF0;
259static constexpr uint8_t SHIFT_SEQ5LOOP = 4;
260static constexpr uint8_t MASK_SEQ6LOOP = 0x0F;
261static constexpr uint8_t SHIFT_SEQ6LOOP = 0;
262
263// ==============================================
264// 0x15 (RW)
265// ==============================================
266// Register : WAVCFG12
267static constexpr uint8_t REG_WAVCFG12 = 0x15;
268static constexpr uint8_t MASK_SEQ7LOOP = 0xF0;
269static constexpr uint8_t SHIFT_SEQ7LOOP = 4;
270static constexpr uint8_t MASK_SEQ8LOOP = 0x0F;
271static constexpr uint8_t SHIFT_SEQ8LOOP = 0;
272
273// ==============================================
274// 0x16 (RW)
275// ==============================================
276// Register : WAVCFG13
277static constexpr uint8_t REG_WAVCFG13 = 0x16;
278static constexpr uint8_t MASK_WAITSLOT = 0x60; // bits 6:5
279static constexpr uint8_t SHIFT_WAITSLOT = 5;
280static constexpr uint8_t MASK_MAINLOOP = 0x0F;
281static constexpr uint8_t SHIFT_MAINLOOP = 0;
282
283// ==============================================
284// 0x18 (RW)
285// ==============================================
286// Register : CONTCFG1
287static constexpr uint8_t REG_CONTCFG1 = 0x18;
288static constexpr uint8_t MASK_EDGE_FRE = 0xF0;
289static constexpr uint8_t SHIFT_EDGE_FRE = 4;
290static constexpr uint8_t MASK_EN_F0_DET = 0x08;
291static constexpr uint8_t MASK_SIN_MODE = 0x01;
292
293// ==============================================
294// 0x19 (RW)
295// ==============================================
296// Register : CONTCFG2
297static constexpr uint8_t REG_CONTCFG2 = 0x19;
298static constexpr uint8_t MASK_F_PRE = 0xFF;
299static constexpr uint8_t SHIFT_F_PRE = 0;
300
301// ==============================================
302// 0x1A (RW)
303// ==============================================
304// Register : CONTCFG3
305static constexpr uint8_t REG_CONTCFG3 = 0x1A;
306static constexpr uint8_t MASK_DRV_WIDTH = 0xFF;
307static constexpr uint8_t SHIFT_DRV_WIDTH = 0;
308
309// ==============================================
310// 0x1C (RW)
311// ==============================================
312// Register : CONTCFG5
313static constexpr uint8_t REG_CONTCFG5 = 0x1C;
314static constexpr uint8_t MASK_BRK_GAIN = 0x0F;
315static constexpr uint8_t SHIFT_BRK_GAIN = 0;
316
317// ==============================================
318// 0x1D (RW)
319// ==============================================
320// Register : CONTCFG6
321static constexpr uint8_t REG_CONTCFG6 = 0x1D;
322static constexpr uint8_t MASK_TRACK_EN = 0x80;
323static constexpr uint8_t MASK_DRV1_LVL = 0x7F;
324static constexpr uint8_t SHIFT_DRV1_LVL = 0;
325
326// ==============================================
327// 0x1E (RW)
328// ==============================================
329// Register : CONTCFG7
330static constexpr uint8_t REG_CONTCFG7 = 0x1E;
331static constexpr uint8_t MASK_DRV2_LVL = 0x7F;
332static constexpr uint8_t SHIFT_DRV2_LVL = 0;
333
334// ==============================================
335// 0x1F (RW)
336// ==============================================
337// Register : CONTCFG8
338static constexpr uint8_t REG_CONTCFG8 = 0x1F;
339static constexpr uint8_t MASK_DRV1_TIME = 0xFF;
340static constexpr uint8_t SHIFT_DRV1_TIME = 0;
341
342// ==============================================
343// 0x20 (RW)
344// ==============================================
345// Register : CONTCFG9
346static constexpr uint8_t REG_CONTCFG9 = 0x20;
347static constexpr uint8_t MASK_DRV2_TIME = 0xFF;
348static constexpr uint8_t SHIFT_DRV2_TIME = 0;
349
350// ==============================================
351// 0x21 (RW)
352// ==============================================
353// Register : CONTCFG10
354static constexpr uint8_t REG_CONTCFG10 = 0x21;
355static constexpr uint8_t MASK_BRK_TIME = 0xFF;
356static constexpr uint8_t SHIFT_BRK_TIME = 0;
357
358// ==============================================
359// 0x22 (RW)
360// ==============================================
361// Register : CONTCFG11
362static constexpr uint8_t REG_CONTCFG11 = 0x22;
363static constexpr uint8_t MASK_TRACK_MARGIN = 0xFF;
364static constexpr uint8_t SHIFT_TRACK_MARGIN = 0;
365
366// ==============================================
367// 0x25 (RO)
368// ==============================================
369// Register : CONTRD14
370static constexpr uint8_t REG_CONTRD14 = 0x25;
371static constexpr uint8_t MASK_F_LRA_F0_H = 0xFF;
372static constexpr uint8_t SHIFT_F_LRA_F0_H = 0;
373
374// ==============================================
375// 0x26 (RO)
376// ==============================================
377// Register : CONTRD15
378static constexpr uint8_t REG_CONTRD15 = 0x26;
379static constexpr uint8_t MASK_F_LRA_F0_L = 0xFF;
380static constexpr uint8_t SHIFT_F_LRA_F0_L = 0;
381
382// ==============================================
383// 0x27 (RO)
384// ==============================================
385// Register : CONTRD16
386static constexpr uint8_t REG_CONTRD16 = 0x27;
387static constexpr uint8_t MASK_CONT_F0_H = 0xFF;
388static constexpr uint8_t SHIFT_CONT_F0_H = 0;
389
390// ==============================================
391// 0x28 (RO)
392// ==============================================
393// Register : CONTRD17
394static constexpr uint8_t REG_CONTRD17 = 0x28;
395static constexpr uint8_t MASK_CONT_F0_L = 0xFF;
396static constexpr uint8_t SHIFT_CONT_F0_L = 0;
397
398// ==============================================
399// 0x2D (RW)
400// ==============================================
401// Register : RTPCFG1
402static constexpr uint8_t REG_RTPCFG1 = 0x2D;
403static constexpr uint8_t MASK_BASE_ADDR_H = 0x0F;
404static constexpr uint8_t SHIFT_BASE_ADDR_H = 0;
405
406// ==============================================
407// 0x2E (RW)
408// ==============================================
409// Register : RTPCFG2
410static constexpr uint8_t REG_RTPCFG2 = 0x2E;
411static constexpr uint8_t MASK_BASE_ADDR_L = 0xFF;
412static constexpr uint8_t SHIFT_BASE_ADDR_L = 0;
413
414// ==============================================
415// 0x2F (RW)
416// ==============================================
417// Register : RTPCFG3
418static constexpr uint8_t REG_RTPCFG3 = 0x2F;
419static constexpr uint8_t MASK_FIFO_AEH = 0xF0;
420static constexpr uint8_t SHIFT_FIFO_AEH = 4;
421static constexpr uint8_t MASK_FIFO_AFH = 0x0F;
422static constexpr uint8_t SHIFT_FIFO_AFH = 0;
423
424// ==============================================
425// 0x30 (RW)
426// ==============================================
427// Register : RTPCFG4
428static constexpr uint8_t REG_RTPCFG4 = 0x30;
429static constexpr uint8_t MASK_FIFO_AEL = 0xFF;
430static constexpr uint8_t SHIFT_FIFO_AEL = 0;
431
432// ==============================================
433// 0x31 (RW)
434// ==============================================
435// Register : RTPCFG5
436static constexpr uint8_t REG_RTPCFG5 = 0x31;
437static constexpr uint8_t MASK_FIFO_AFL = 0xFF;
438static constexpr uint8_t SHIFT_FIFO_AFL = 0;
439
440// ==============================================
441// 0x32 (RW)
442// ==============================================
443// Register : RTPDATA
444static constexpr uint8_t REG_RTPDATA = 0x32;
445static constexpr uint8_t MASK_RTP_DATA = 0xFF;
446static constexpr uint8_t SHIFT_RTP_DATA = 0;
447
448// ==============================================
449// 0x33 (RW)
450// ==============================================
451// Register : TRGCFG1
452static constexpr uint8_t REG_TRGCFG1 = 0x33;
453static constexpr uint8_t MASK_TRG1_POS = 0x80;
454static constexpr uint8_t MASK_TRG1SEQ_P = 0x7F;
455static constexpr uint8_t SHIFT_TRG1SEQ_P = 0;
456
457// ==============================================
458// 0x36 (RW)
459// ==============================================
460// Register : TRGCFG4
461static constexpr uint8_t REG_TRGCFG4 = 0x36;
462static constexpr uint8_t MASK_TRG1_NEG = 0x80;
463static constexpr uint8_t MASK_TRG1SEQ_N = 0x7F;
464static constexpr uint8_t SHIFT_TRG1SEQ_N = 0;
465
466// ==============================================
467// 0x39 (RW)
468// ==============================================
469// Register : TRGCFG7
470static constexpr uint8_t REG_TRGCFG7 = 0x39;
471static constexpr uint8_t MASK_TRG1_POLAR = 0x80;
472static constexpr uint8_t MASK_TRG1_LEV = 0x40;
473static constexpr uint8_t MASK_TRG1_BRK = 0x20;
474
475// ==============================================
476// 0x3A (RW)
477// ==============================================
478// Register : TRGCFG8
479static constexpr uint8_t REG_TRGCFG8 = 0x3A;
480static constexpr uint8_t MASK_TRG1_MODE = 0x18; // bits 4:3
481static constexpr uint8_t SHIFT_TRG1_MODE = 3;
482static constexpr uint8_t MASK_TRG1_STOP = 0x04;
483
484// ==============================================
485// 0x3C (RW)
486// ==============================================
487// Register : GLBCFG2
488static constexpr uint8_t REG_GLBCFG2 = 0x3C;
489static constexpr uint8_t MASK_START_DLY = 0xFF;
490static constexpr uint8_t SHIFT_START_DLY = 0;
491
492// ==============================================
493// 0x3E (RW)
494// ==============================================
495// Register : GLBCFG4
496static constexpr uint8_t REG_GLBCFG4 = 0x3E;
497static constexpr uint8_t MASK_GO_PRIO = 0xC0; // bits 7:6
498static constexpr uint8_t SHIFT_GO_PRIO = 6;
499static constexpr uint8_t MASK_TRG1_PRIO = 0x03; // bits 1:0
500static constexpr uint8_t SHIFT_TRG1_PRIO = 0;
501
502// ==============================================
503// 0x3F (RO)
504// ==============================================
505// Register : GLBRD5
506static constexpr uint8_t REG_GLBRD5 = 0x3F;
507static constexpr uint8_t SHIFT_GLB_STATE = 0;
508
509// ==============================================
510// 0x40 (RW)
511// ==============================================
512// Register : RAMADDRH
513static constexpr uint8_t REG_RAMADDRH = 0x40;
514static constexpr uint8_t MASK_RAMADDRH = 0x0F;
515static constexpr uint8_t SHIFT_RAMADDRH = 0;
516
517// ==============================================
518// 0x41 (RW)
519// ==============================================
520// Register : RAMADDRL
521static constexpr uint8_t REG_RAMADDRL = 0x41;
522static constexpr uint8_t MASK_RAMADDRL = 0xFF;
523static constexpr uint8_t SHIFT_RAMADDRL = 0;
524
525// ==============================================
526// 0x42 (RW)
527// ==============================================
528// Register : RAMDATA
529static constexpr uint8_t REG_RAMDATA = 0x42;
530static constexpr uint8_t MASK_RAMDATA = 0xFF;
531static constexpr uint8_t SHIFT_RAMDATA = 0;
532
533// ==============================================
534// 0x43 (RW)
535// ==============================================
536// Register : SYSCTRL1
537static constexpr uint8_t REG_SYSCTRL1 = 0x43;
538static constexpr uint8_t MASK_VBAT_MODE = 0x80;
539static constexpr uint8_t MASK_EN_RAMINIT = 0x08;
540static constexpr uint8_t MASK_EN_FIR = 0x04;
541
542// ==============================================
543// 0x44 (RW)
544// ==============================================
545// Register : SYSCTRL2
546static constexpr uint8_t REG_SYSCTRL2 = 0x44;
547static constexpr uint8_t MASK_WAKE = 0x80;
548static constexpr uint8_t MASK_STANDBY = 0x40;
549static constexpr uint8_t MASK_INTN_PIN = 0x08;
550static constexpr uint8_t MASK_WAVDAT_MODE = 0x03;
551static constexpr uint8_t SHIFT_WAVDAT_MODE = 0;
552
553// ==============================================
554// 0x49 (RW)
555// ==============================================
556// Register : SYSCTRL7
557static constexpr uint8_t REG_SYSCTRL7 = 0x49;
558static constexpr uint8_t MASK_GAIN_BYPASS = 0x40;
559static constexpr uint8_t MASK_D2S_GAIN = 0x07;
560static constexpr uint8_t SHIFT_D2S_GAIN = 0;
561
562// ==============================================
563// 0x4C (RW)
564// ==============================================
565// Register : PWMCFG1
566static constexpr uint8_t REG_PWMCFG1 = 0x4C;
567static constexpr uint8_t MASK_PRC_EN = 0x80;
568static constexpr uint8_t MASK_PRCTIME = 0x7F;
569static constexpr uint8_t SHIFT_PRCTIME = 0;
570
571// ==============================================
572// 0x4D (RW)
573// ==============================================
574// Register : PWMCFG2
575static constexpr uint8_t REG_PWMCFG2 = 0x4D;
576static constexpr uint8_t MASK_PD_HWM = 0x10; // shutdown half wave modulate
577
578// ==============================================
579// 0x4E (RW)
580// ==============================================
581// Register : PWMCFG3
582static constexpr uint8_t REG_PWMCFG3 = 0x4E;
583static constexpr uint8_t MASK_PR_EN = 0x80;
584static constexpr uint8_t MASK_PRLVL = 0x7F;
585static constexpr uint8_t SHIFT_PRLVL = 0;
586
587// ==============================================
588// 0x4F (RW)
589// ==============================================
590// Register : PWMCFG4
591static constexpr uint8_t REG_PWMCFG4 = 0x4F;
592static constexpr uint8_t MASK_PRTIME = 0xFF;
593static constexpr uint8_t SHIFT_PRTIME = 0;
594
595// ==============================================
596// 0x51 (RW)
597// ==============================================
598// Register : DETCFG1
599static constexpr uint8_t REG_DETCFG1 = 0x51;
600static constexpr uint8_t MASK_RL_OS = 0x10;
601static constexpr uint8_t MASK_CLK_ADC = 0x07;
602static constexpr uint8_t SHIFT_CLK_ADC = 0;
603
604// ==============================================
605// 0x52 (RW)
606// ==============================================
607// Register : DETCFG2
608static constexpr uint8_t REG_DETCFG2 = 0x52;
609static constexpr uint8_t MASK_VBAT_GO = 0x02;
610static constexpr uint8_t MASK_DIAG_GO = 0x01;
611
612// ==============================================
613// 0x53 (RO)
614// ==============================================
615// Register : DET_RL
616static constexpr uint8_t REG_DET_RL = 0x53;
617static constexpr uint8_t MASK_RL = 0xFF;
618static constexpr uint8_t SHIFT_RL = 0;
619
620// ==============================================
621// 0x55 (RO)
622// ==============================================
623// Register : DET_VBAT
624static constexpr uint8_t REG_DET_VBAT = 0x55;
625static constexpr uint8_t MASK_VBAT = 0xFF;
626static constexpr uint8_t SHIFT_VBAT = 0;
627
628// ==============================================
629// 0x57 (RO)
630// ==============================================
631// Register : DET_LO
632static constexpr uint8_t REG_DET_LO = 0x57;
633static constexpr uint8_t MASK_VBAT_LO = 0x30; // bits 5:4
634static constexpr uint8_t SHIFT_VBAT_LO = 4;
635static constexpr uint8_t MASK_RL_LO = 0x03; // bits 1:0
636static constexpr uint8_t SHIFT_RL_LO = 0;
637
638// ==============================================
639// 0x54 (RO)
640// ==============================================
641// Register : DET_OS
642static constexpr uint8_t REG_DET_OS = 0x54;
643static constexpr uint8_t MASK_OS = 0xFF;
644static constexpr uint8_t SHIFT_OS = 0;
645
646// ==============================================
647// 0x5A (RW)
648// ==============================================
649// Register : TRIMCFG3
650static constexpr uint8_t REG_TRIMCFG3 = 0x5A;
651static constexpr uint8_t MASK_TRIM_LRA = 0x3F;
652static constexpr uint8_t SHIFT_TRIM_LRA = 0;
653
654// ==============================================
655// 0x64 (RO)
656// ==============================================
657// Register : CHIPID
658static constexpr uint8_t REG_CHIPID = 0x64;
659static constexpr uint8_t MASK_CHIPID_H = 0x40;
660static constexpr uint8_t MASK_CHIPID_L = 0x01;
661
662// ==============================================
663// 0x77 (RW)
664// ==============================================
665// Register : ANACFG8
666static constexpr uint8_t REG_ANACFG8 = 0x77;
667static constexpr uint8_t MASK_TRTF_CTRL_HDRV = 0xC0; // bits 7:6
668static constexpr uint8_t SHIFT_TRTF_CTRL_HDRV = 6;
669
670} // namespace AW86224Regs